@article{3035105,
    title = "High-Performance COTS FPGA SoC for Parallel Hyperspectral Image Compression with CCSDS-123.0-B-1",
    author = "Tsigkanos, A. and Kranitis, N. and Theodoropoulos, D. and Paschalis, A.",
    journal = "IEEE Transactions on Very Large Scale Integration (VLSI) Systems",
    year = "2020",
    volume = "28",
    number = "11",
    pages = "2397-2409",
    publisher = "Institute of Electrical and Electronics Engineers, Inc. (IEEE)",
    doi = "10.1109/TVLSI.2020.3020164",
    keywords = "Bandwidth compression;  Commercial off-the-shelf;  Digital image storage;  Field programmable gate arrays (FPGA);  Hyperspectral imaging;  Image compression;  Image segmentation;  Pixels;  Programmable logic controllers;  Remote sensing;  Spectroscopy, Commercial-off-the-shelf parts;  Hyperspectral compression;  Hyperspectral sensors;  Parallel implementations;  Remote sensing technology;  Seamless integration;  System-on-chip devices;  Throughput performance, System-on-chip",
    abstract = "Nowadays, hyperspectral imaging is recognized as a cornerstone remote sensing technology. Next generation, high-speed airborne, and space-borne imagers have increased resolution, resulting in an explosive growth in data volume and instrument data rate in the range of gigapixel per second. This competes with limited on-board resources and bandwidth, making hyperspectral image compression a mission critical on-board processing task. At the same time, the 'new space' trend is emerging, where launch costs decrease, and agile approaches are exploited building smallsats using commercial-off-the-shelf (COTS) parts. In this contribution, we introduce a high-performance parallel implementation of the CCSDS-123.0-B-1 hyperspectral compression algorithm targeting SRAM field-programmable gate array (FPGA) technology. The architecture exploits image segmentation to provide the robustness to data corruption and enables scalable throughput performance by leveraging segment-level parallelism. Furthermore, we exploit the capabilities of a COTS FPGA system-on-chip (SoC) device to optimize size, weight, power, and cost (SWaP-C). The architecture partitions a hyperspectral cube stored in a DRAM framebuffer into segments, compressing them in parallel using a flexible software scheduler hosted in the SoC CPU and several compressor accelerator cores in the FPGA fabric. A 5-core implementation demonstrated on a Zynq-7045 FPGA achieves a throughput performance of 1387 Msamples/s [22.2 Gb/s at 16 bits per pixel per band (bpppb)] and outperforms previous implementations in equivalent FPGA technology, allowing seamless integration with next-generation hyperspectral sensors. © 1993-2012 IEEE."
}