TY - JOUR
TI - Design of a Real-Time DSP Engine on RF-SoC FPGA for 5G Networks
AU - Kitsakis, V.
AU - Kanta, K.
AU - Stratakos, I.
AU - Giannoulis, G.
AU - Apostolopoulos, D.
AU - Lentaris, G.
AU - Avramopoulos, H.
AU - Soudris, D.
AU - Reisis, D.I.
JO - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
PY - 2020
VL - 11616 LNCS
TODO - null
SP - 540-551
PB - Springer-Verlag
SN - null
TODO - 10.1007/978-3-030-38085-4_46
TODO - 5G mobile communication systems;  Digital signal processing;  Fiber optic networks;  Field programmable gate arrays (FPGA);  Frequency allocation;  Network architecture;  Queueing networks;  System-on-chip, DSP architectures;  Implementation cost;  Parallelizing;  Proposed architectures;  Real time performance;  Real-time DSP;  Sampling frequency offset;  Wireless communications, Integrated circuit design
TODO - 5G advances the wireless communications by providing a significant improvement to the data rate, capability of connected devices and data volumes compared to the previous generations. While these advantages combine along with a wider range of applications to merit the end-user, the technologies to be used are not specified. Considering this problem and in order to efficiently support the 5G deployment researchers and engineers turned their attention on FPGA base band architectures that keep the implementation cost relatively low and at the same time they are reprogramable to provide solutions to the emerging requirements and their consequent modifications. Aiming at the contribution to the 5G technologies the current paper introduces the design of a base band DSP architecture that targets the required real time performance. Moreover, the proposed architecture is scalable by efficiently parallelizing and/or pipelining the corresponding data paths. The paper presents the pilot FPGA designs of the IFFT/FFT and Sampling Frequency Offset (SFO) functions that achieve a 500 Msps performance on a RF-SoC Xilinx ZCU111 board. © 2020, IFIP International Federation for Information Processing.
ER -