TY - JOUR
TI - Ldpc hardware acceleration in 5g open radio access network platforms
AU - Papatheofanous, E.A.
AU - Reisis, D.
AU - Nikitopoulos, K.
JO - IEEE Access
PY - 2021
VL - 9
TODO - null
SP - 152960-152971
PB - Institute of Electrical and Electronics Engineers, Inc. (IEEE)
SN - 2169-3536
TODO - 10.1109/ACCESS.2021.3127039
TODO - 5G mobile communication systems;  Acceleration;  Decoding;  Digital radio;  Digital signal processing;  Logic gates;  Memory architecture;  Network architecture;  Network layers;  Open source software;  Open systems;  Radio;  Radio access networks;  Software radio, 5g new radio;  Accelerator;  Field-programmable gate array;  Hardware acceleration;  Low density parity check;  Low-density parity-check;  Network platforms;  Radio access network;  Radio access networks;  Radio networks, Field programmable gate arrays (FPGA)
TODO - The Open Radio Access Network (RAN) concept has been gaining wide acceptance in recent network architectures, including 5G New Radio (NR) network deployments. Current Open RAN radio implementation efforts, aim at integrating several white-box hardware elements and executing digital processing on open-source software. When building such a software-based, 5G Open RAN platform, challenges include achieving real-time execution times for demanding computational blocks of the 5G NR physical layer processing, such as Low Density Parity Check (LDPC) decoding. In this context, having already identified both the capabilities as well as the challenges that Field-programmable Gate Arrays (FPGAs) offer for accelerating LDPC, we present our novel LDPC FPGA accelerator system. In this paper, we contribute the implementation details of our FPGA accelerator design as well as the process of integrating the accelerator with OpenAirInterface (OAI), the basis for our 5G NR platform. For the first time in the literature, we show an FPGA-based LDPC accelerator fully integrated with a complete software platform, that is able to achieve more than $1.6Gbps$ decoding throughput and up to 13 times faster execution times compared to single core software implementations. Finally, in our results, we show that LDPC encoding is more challenging to accelerate due to lower computational complexity. © 2021 IEEE.
ER -