TY - JOUR
TI - Development and Testing on the European Space-Grade BRAVE FPGAs: Evaluation of NG-Large Using High-Performance DSP Benchmarks
AU - Leon, V.
AU - Stamoulias, I.
AU - Lentaris, G.
AU - Soudris, D.
AU - Gonzalez-Arjona, D.
AU - Domingo, R.
AU - Codinachs, D.M.
AU - Conway, I.
JO - IEEE Access
PY - 2021
VL - 9
TODO - null
SP - 131877-131892
PB - Institute of Electrical and Electronics Engineers, Inc. (IEEE)
SN - 2169-3536
TODO - 10.1109/ACCESS.2021.3114502
TODO - Application programs;  Benchmarking;  Computer hardware description languages;  Data transfer;  Digital signal processing;  Hardening;  Integrated circuit design;  Logic gates;  Memory architecture;  Program processors;  Radiation hardening;  Random access storage;  Space applications, Assessment methodologies;  Benchmark testing;  Europe;  European field-programmable gate array;  HW benchmarking;  Nanoxplore;  Performance;  Radiation-hardened;  Random access memory;  Tool testing, Field programmable gate arrays (FPGA)
TODO - The advent of space applications with increased computational requirements has led the space industry to consider innovative chips and avionics architectures for high-performance on-board data processing. In a relatively limited market, the European BRAVE family of Field-Programmable Gate Arrays (FPGAs) offers such novel radiation-hardened solutions. Towards verification, the current work devises and applies a methodology to thoroughly assess the BRAVE FPGAs and their SW tools. The paper focuses on NG-Large, i.e., the largest FPGA of the 65nm Radiation-Hardened-By-Design (RHBD) technology of NanoXplore to date. The proposed approach comprises a number of customized steps to systematically evaluate the entire FPGA design flow. Initially, we carefully select and tune a set of high-performance Digital Signal Processing (DSP) Computer Vision (CV) benchmarks, which were originally developed as Hardware Description Language (HDL) IPs in past projects of the European Space Agency (ESA). Subsequently, we perform exhaustive exploration of the Synthesis, Placement, and Routing stages of the SW tools, as well as testing on actual HW boards. At each step, we generate and analyze a variety of results, while we also compare them to 3rd-party solutions. The results show that NG-Large provides sufficient programmability and performance, e.g., classic CV IPs for feature detection on megapixel images can achieve a throughput of 5-10 frames per second, while the on-chip memory utilization is up to 56% better than that of 3rd-party FPGAs. As a highlight, at system-level, we successfully implement and execute an entire HW/SW algorithmic pipeline for Vision-Based Navigation (VBN) involving SpaceWire data transfers with LEON CPU NG-Large co-processing. © 2013 IEEE.
ER -