TY - CONF
TI - FPGA-based architecture for real-time IP video and image compression
AU - Maroulis, D.
AU - Sgouros, N.
AU - Chaikalis, D.
PY - 2006
SP - 5579+
PB - IEEE Comput. Soc
T2 - 2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11,
PROCEEDINGS
TODO - 10.1109/ISCAS.2006.1693899
TODO - null
TODO - Three-dimensional imaging applications require high resolution images
that finally result in high data volumes. Due to bandwidth and storage
restrictions, an efficient and robust compression scheme must be
developed in order to overcome these limitations. This work presents a
hardware implementation of a real-time disparity estimation scheme
targeted but not limited to Integral Photography (IP) 3D imaging
applications. The proposed system demonstrates an efficient architecture
which copes with the increased bandwidth demands that 3D imaging
technology requires. Moreover, the system can successfully process high
resolution IP video sequences in real-time.
ER -