TY - CONF
TI - Measuring and Exploiting Guardbands of Server-Grade ARMv8 CPU Cores and
DRAMs
AU - Tovletoglou, Konstantinos
AU - Mukhanov, Lev
AU - Karakonstantis, Georgios
AU - and Chatzidimitriou, Athanasios
AU - Papadimitriou, George and
AU - Kaliorakis, Manolis
AU - Gizopoulos, Dimitris
AU - Zacharias and
AU - Hadjilambrou
AU - Sazeides, Yiannakis
AU - Lampropulos, Alejandro
AU - Das,
AU - Shidhartha
AU - Phong Vo
PY - 2018
SP - 6-9
PB - IEEE Comput. Soc
T2 - 2018 48TH ANNUAL IEEE/IFIP INTERNATIONAL CONFERENCE ON DEPENDABLE
SYSTEMS AND NETWORKS WORKSHOPS (DSN-W)
TODO - 10.1109/DSN-W.2018.00013
TODO - null
TODO - In this paper, we present the results of our comprehensive measurement
study of the timing and voltage guardbands in memories and cores of a
commodity ARMv8 based micro-server. Using various synthetic
micro-benchmarks, we reveal how the adopted voltage margins vary among
the 8 cores of the CPU chip, and among 3 different sigma chips and we
show how prone they are to worst-case voltage noise. In addition, we
characterize the variation of ‘weak’ DRAM cells in terms of their
retention time across 72 DRAM chips and evaluate the error mitigation
efficacy of the available error-correcting codes in case of operation
under aggressively relaxed refresh periods. Finally, we show the overall
energy savings that could be achieved by shaving the adopted guardbands
in the cores and memories using various applications. Our
characterization results show the potential to obtain up-to 38.8%
energy savings in cores and up-to 27.3% within DRAMs.
ER -