Summary:
The current dissertation contributes in designing efficient parallel
architectures
for image, video and graphics applications. The main objective is
to organize parallel memories for supporting the most common algorithmic
requirements encountered in the certain scientific field. Moreover, as a case
study, the dissertation focuses on the implementation of motion estimation
algorithms for video compression.
An elaborate study of bibliography related to both of the above objectives
precedes the design of a programmable architecture executing a variety
of block-matching algorithms with real-time performance. The design
involves a parallel memory for the local storage of pixels, parallel arithmetic
units for the examination of candidate blocks, and an application-specific
instruction-set processor to meet the computational requirements of each
algorithm. Overall, the architecture bases on pipelining techniques and data
level parallelism to speed-up the block matching procedure. It introduces a
novel instruction set and a speculative execution technique, which leads in
almost 100% utilization of the data-path by allowing the algorithm to operate
concurrently with the examination of candidate blocks. The cost and the
performance of the reconfigurable motion estimation module are evaluated
on FPGA platforms. Comparison to similar works of the literature highlights
the advantages and verifies the efficiency of the proposed design.
Furthermore, the dissertation considers the problem of storing and retrieving
pixels in parallel for a wider range of graphics applications. It introduces
a technique tackling this problem and leading to an efficient memory
organization, which facilitates parallel processing by allowing any algorithm
to access numerous pixels in a single cycle. The solution involves a non-linear
skew function to map each image pixel in one out of B memory banks.
The proposed mapping supports the most common graphics requirements by
achieving parallel access to rows, columns, rectangles, and sparse sets of
pixels
originating at any location on the image. Overall, the organization utilizes
less memory banks compared to the corresponding solutions of the literature,
which use B>E when E pixels are requested in parallel. In contrast to
the common bibliographic approach using prime –or other peculiar– numbers
for B, the proposed solution organizes the memory with only B=E banks
allowing B to be any power of 2. Moreover, based on the properties of its
mapping function, the solution exploits successive request correlations during
image/video processing to handle possible memory conflicts by spending only
one cycle every B memory accesses. The resulting organization improves the
resource utilization, reduces the hardware cost and leads to efficient parallel
memory designs. The dissertation presents theorems and proofs regarding
the properties of the proposed mapping function and the conflict handling
technique. Subsequently, it analyzes the performance of the novel memory
in example applications to show the merit of the proposed organization and
to compare with hitherto published solutions at the implementation level. In
this direction, the analysis also includes the integration of the novel memory
to the developed motion estimation architecture; the results show improved
performance/cost for the entire estimator and quantify the benefits of the
proposed memory in terms of hardware resources.
Keywords:
Parallel architectures, Parallel memory organization, Image/video processing, Motion estimation
