Summary:
The FPGA implementation of LDPC encoders for channel codes standardized by
CCSDS for space communication applications is described in this work.
CCSDS suggests two classes of channel codes for telemetry applications: one for
near-earth and another for deep-space communications, each one optimized for
the demands of the specific field. In both cases, the specification concerns
linear block codes with large block size and sparse generator matrices.
Regarding near-earth codes, the specification describes a Euclidean geometry
based (8160,7136) LDPC code at rate 7/8, while in the deep-space case, 9 codes
are defined which are the combination of thee block lengths (1024,4096,16384
bits) with three rates (½, 2/3, 4/5), sharing a common mathematical
description. This fact enables the VHDL description of a common encoder for all
of them.
The generator matrices of these codes possess considerable structure which
facilitates implementation. Concerning deep-space codes generator matrices,
parallelism extends over two dimensions, which can be exploited concurrently to
optimize timing performance and at the same time minimize resource utilization.
The price to be paid however is increased latency, which can be mitigated by
the pipelined operation of the output interface. VHDL description of the
encoder is generic, allowing the easy modification of the code parameters
(block size, rate), the amount of parallelism in each dimension and the
input-output bus width, leading to different performance-latency balances.
Also in the case of the near-earth code, an efficient design of the encoder's
sub-entities is described, leading to resources utilization optimizations,
compared to existing implementations. The encoder in this case is designed for
16-bit input-output bus.
All described encoders input-output is performed on AMBA AXI-4 Stream compliant
interfaces, facilitating their integration in an embedded system's design and
communication with standard FIFO interfaces. The encoders' operation is optimal
in that an uninterrupted flow of data is provided on the output interface,
without idle cycles. The only exception is the near-earth encoder for which
just one idle cycle every 513 is inserted.
The correctness of the VHDL description's is validated by functional simulation
for all supported cases, where 100% code coverage is demanded. The verification
plan includes also the demonstration of real-time operation of the encoders in
an integrated system implemented on a XUPV505-LX110T development board, where
the actual performance of the encoders is recorded and lies in the multi-Gbps
range. Finally, the proposed encoders are shown to be the fastest
stream-oriented implementations for the specified family of LDPC codes, with
minimal resource utilization.
Keywords:
LDPC, CCSDS, FPGA, near-earth, deep-space
