Dissertation committee:
Τσίλης Μανώλης, Επικ. Καθ. ΕΚΠΑ
Ρεΐσης Διονύσης, Αν. Καθ. ΕΚΠΑ
Κατσάγγελος Άγγελος, Καθ. ΕΚΠΑ
Πολύδωρος Ανδρέας, Καθ. ΕΚΠΑ
Μανωλάκος Ηλίας, Καθ. ΕΚΠΑ
Σούντρης Δημήτριος, Αν. Καθ. ΕΜΠ
Νικιτόπουλος Κωνσταντίνος, Επικ. Καθ. Παν. Surrey (UK)
Summary:
Multiple-Input Multiple-Output (MIMO) communication is a rapidly developing wireless technology which promises increased data-rates and link reliability with mobility and high quality-of-service (QoS) for multiple users. Several antennas at both transmitter and receiver increase the channel capacity with efficient bandwidth utilization, due to multiple data transmission over the same frequency bands. MIMO technologies, in combination with the Orthogonal Frequency Division Multiplexing (OFDM) modulation, have been adopted by many wireless standards such as WiFi (IEEE-802.11n/ac), Long Term Evolution (3GPP-LTE) and WiMAX (IEEE-802.16e) and they expected to play a key role in the upcoming WiFi (IEEE-802.11ax) standard and in the fifth generation (5G) mobile phone systems. Nevertheless, the advantages provided by MIMO technologies come at the expense of a substantial increase in the complexity mainly of the receiver, but in some cases also in the transmitter side, which has a major impact on the implementation cost and power consumption of MIMO-OFDM systems.
The modern integrated circuits has increased transistor capacity due to the advanced sub-micron technology, which provide the flexibility to design a single chip to support multiple protocols, with a Software Defined Radio (SDR) architecture. In a SDR system the computational intensive and time-critical processes are mapped to hardware accelerator units, which should have various operational modes and run-time reconfigurations to support the system requirements of multiple protocols. Furthermore, these hardware units should have increased scalability, low complexity and implementation cost and reduced power consumption to support SDR systems running on battery. Therefore, the design of low-complexity and power optimal SDR and MIMO architectures is an important issue, which is tackled throughout this thesis.
The first part of this dissertation presents the state of the art FFT architectures for OFDM systems with multiple data streams (MIMO-OFDM). A detailed analysis in terms of complexity, scalability, implementation cost and power consumption is presented and the possibility of SDR support is investigated, for these architectures. A novel memory-based FFT architecture is proposed with increased scalability and support for operation on advanced SDR systems. The efficient conflict-free addressing scheme reduces the complexity of the interconnection network and the memory requirements of the FFT processor, resulting in a low implementation cost and power consumption, even in the case of continuous-flow operation. The reconfigurable architecture can be tailored to match any SDR system requirements, while a scheduling mechanism can be used to optimize the processing latency of the FFT processor, based on run-time parameters.
In the second part of this thesis MIMO detection architectures are investigated, in terms of complexity and error-rate performance. The computationally intensive task of tree node enumeration on sphere decoders is analyzed and the state of the art algorithms are presented, for the cases of hard decision detection and detection with the use of soft information. An advanced enumeration technique is proposed, for hard or soft sphere decoders, which can guarantee the optimal detection for all scenarios and channel conditions. The proposed method is based on a predefined visiting order, a single distance
calculation unit and a tuned pruning metric, which increases the number of visiting nodes but with low computational requirements per node and reduced total complexity, for the detection process. The architecture of the proposed method is presented and the ASIC and FPGA implementation is compared with implementations of the state of the art optimal enumeration algorithms. The efficient architecture of the proposed technique leads to reduced implementation cost and power consumption, resulting in its potential use in more complex MIMO-OFDM systems.
Keywords:
Real-Time MIMO Baseband Architectures, FFT processor, Parallel FFT Architectures, MIMO Detection, Sphere Decoder
