Summary:
This dissertation focuses on the study of digital architectures and processors
organization, leading to the efficient instruction execution, while enhancing
the parallelization of applications. First, we present a configurable
System-on-Chip multiprocessor, for speeding up MPEG-2 and MPEG-4 encoding, by
using thread-level parallelism. Improving the performance of the MPEG encoders
is shown by reducing the dynamic instruction count at multiple processor
contexts. Next, we present the design and implementation of FFT architectures
for 4K, 16K, 64K and 256K complex points, which are based on utilizing a novel
radix-43 engine. The architectures have been implemented both on FPGAs and
VLSI, achieving significantly high operating frequencies and throughput.
Comparing the main characteristics and the performance of the 4K FFT
architecture, with existing solutions in the literature, we prove the
efficiency and the advantages of the proposed solution for implementing FFT
architectures. Finally, the last part of the thesis presents a multiple
precision floating-point multiplier and three floating-point Fused Multiply-Add
architectures. The proposed designs can accommodate multiple IEEE precision
formats, and perform parallel operations of stand-alone multiplications and
additions, or execute in parallel multiple single instruction equations (AxB +
C).
Keywords:
Processor, FFT, Floating-point, FPGA, VLSI
