Summary:
The XGPON (10 Gbps Passive Optical Network) telecommunications protocol of
ITU-T (International Telecommunications Union - Telecommunications
Standardization Sector) is the evolution of the previous GPON, in the data
layer section. The appropriate equipment located closest to the user is the ONU
(Optical Network Unit), and what follows closest to the respective
telecommunications centre is the OLT (Optical Line Termination). In the context
of a group project, we designed in hardware description language and checked
the functionality by programming onto an FPGA of an ONU unit. This work
presents a sub-unit of an ONU, the part that deals with the upstream data flow,
covering what is stated by the protocol in the service adaptation and framing
sublayers.
The protocol defines two hierarchical data layers where upstream is concerned.
The data which flow upwards from the user to the ONU, through Ethernet, are
stored in T-Cont memories, and constitute the lowest layer. In each time
segment that the ONU sends data to the OLT, their origin and size are defined
by the digital field allocation BWmap (Bandwidth map) that the OLT has
previously sent to the downstream. BWmap defines the data volume that is to be
sent to the next packet (upstream XGTC frame) from each T-Cont, and constitutes
the highest hierarchical data layer.
One design choice of the project is the addition of an intermediate data
layer, which will lead sequences of data to be extracted from the memories
based on address, sequence size, possible repeat, and choice of scrambling.
Whereas the previous layer simply defines a data volume, the intermediate one
constructs instructions after having searched and accordingly concatenated the
upstream data in the form of XGEM frames one by one, as well as other mandatory
information like headers and encodings. This choice allows, with minimum
hardware utilisation, to avoid using extra memory that will from the start
store the data from the lowest layer in their entirety.
The basic design units are the ones that transit from one data layer to the
other. A finite state machine (FSM), named scanner, reads the BWmap and checks
when the data volume requested is covered, as it accumulates XGEM frames. This
way, it constructs the instructions of the second data layer. This is a fast
process because XGEM frames are memory mapped during their input. The remainder
is added in the appropriate volume as an idle XGEM frame. Another FSM, called
microsequencer, when the time for data transmission comes, reads the second
data layer and, in real time, extracts the data sequences these instructions
describe.
There are other units within the design. They are the data memories
themselves, the memories where the previous ones are mapped, the instruction
memory of the second layer, the Look-Up Table (LUT) than binds alloc-IDs to
internal T-Cont chip select signals, a down counter for the correct data
transmission timing, and encoding units (CRC, HEC, BIP).
Keywords:
XGPON, ONU, VHDL, FPGA, Networking protocol
