Unit:
Κατεύθυνση Σχεδίασης Ολοκληρωμένων ΚυκλωμάτωνΠληροφορική
Author:
Gerakaris Dimitris-Foivos
Supervisors info:
Πασχάλης Αντώνιος, Καθηγητής. Πληροφορικής και Τηλεπικοινωνιών
Original Title:
Υλοποίηση σε Tεχνολογία Zynq FPGA της Μονάδας Rasterizer ως Επιταχυντή Υλικού με τη χρήση του Vivado HLS της XILINX
Translated title:
Gpu Rasterizer accelerator implementation for Zynq FPGA platform using Xilinx Vivado HLS
Summary:
The purpose of this Thesis is to declare and explain the different algorithms around
Computer Graphics focusing mainly on rasterization rendering technique and explore the
effectiveness of Vivado HLS in rapid graphics rasterization algorithms development. The
goal is to be able to produce exact or similar results with company’s commercial
rasterizer. After the successful implementation, much faster simulation is possible, along
with the ability of easy implementation of new algorithms. The whole process designed to
be implemented and integrated automatically in the company’s toolchain.
Main subject category:
Technology - Computer science
Keywords:
Image, graphics, rasterizer, Vivado HLS, algorithms
