Multiplication in VHDL

Postgraduate Thesis uoadl:2924265 136 Read counter

Unit:
Κατεύθυνση Ηλεκτρονικός Αυτοματισμός (Η/Α, με πρόσθετη εξειδίκευση στην Πληροφορική και στα πληροφοριακά συστήματα)
Library of the School of Science
Deposit date:
2020-10-08
Year:
2020
Author:
Karakelles Anastasios
Supervisors info:
Εμμανουήλ Τσίλης, Επίκουρος Καθηγητής Τμήμα Φυσικής ΕΚΠΑ (κύριος επιβλέπων)
Διονύσιος Ρεΐσης, Αναπληρωτής Καθηγητής Τμήμα Φυσικής ΕΚΠΑ
Γεώργιος Αλεξάκης, Επίκουρος Καθηγητή Τμήμα Φυσικής ΕΚΠΑ
Original Title:
Πολλαπλασιαστές σε VHDL
Languages:
Greek
Translated title:
Multiplication in VHDL
Summary:
The aim of the thesis is the demonstration and the analysis of integrated systems that carry out multiplication with numbers. Various types of multiplier structures are being presented and the specification of each are thorough analyzed. Thereafter, a thorough report is analyzed on the descriptive language, named VHDL, and various examples of circuit simulations are given along with their respective waveforms. Finally, structural diagrams and the corresponding code are being shown of various signed and non signed multipliers.
Main subject category:
Science
Other subject categories:
Technology - Computer science
Keywords:
Multipliers, VHDL, Simulation
Index:
No
Number of index pages:
0
Contains images:
No
Number of references:
14
Number of pages:
78
File:
File access is restricted only to the intranet of UoA.

ΠΟΛΛΑΠΛΑΣΙΑΣΤΕΣ ΣΕ VHDL.pdf
2 MB
File access is restricted only to the intranet of UoA.