Unit:
Department of PhysicsLibrary of the School of Science
Dissertation committee:
Διονύσιος Ρεΐσης, Καθηγητής, Τμήμα Φυσικής, ΕΚΠΑ
Έκτορας Νισταζάκης, Καθηγητής, Τμήμα Φυσικής, ΕΚΠΑ
Άννα Τζανακάκη, Αναπληρώτρια Καθηγήτρια, Τμήμα Φυσικής, ΕΚΠΑ
Δημήτριος Σούντρης, Καθηγητής, Σχολή ΗΜΜΥ, ΕΜΠ
Αντώνης Πασχάλης, Καθηγητής, Τμήμα Πληροφορικής και Τηλεπικοινωνιών, ΕΚΠΑ
Γεώργιος Τόμπρας, Καθηγητής, Τμήμα Φυσικής, ΕΚΠΑ
Μάρκος Αναστασόπουλος, Αναπληρωτής Καθηγητής, Τμήμα Φυσικής, ΕΚΠΑ
Original Title:
Efficient Design Techniques of Switches for Optical Networks and Data Centers
Translated title:
Efficient Design Techniques of Switches for Optical Networks and Data Centers
Summary:
The latest design approach for Data Centers follows the direction of exploiting optical
switching to interconnect Top-of-Rack (ToR) switches that serve thousands of data storing
and computing devices. Optical switching provided the means for the development
of Data Centers with high throughput interconnection networks. A significant contribution
to the advanced optical Data Centers designs is the Nephele architecture that employs
optical data planes, optical Points of Delivery (PoD) switches and ToR switches
equipped with 10 Gbps connections to the PoDs and the servers. Nephele follows the
Software Defined Network (SDN) paradigm based on the OpenFlow protocol and it employs
an Agent communicating the protocol commands to the data plane. A ToR’s usual
function is the Virtual Output Queues (VOQs), which is the prevalent solution for the
head-of-line blocking problem of the Data Center switches. An effective VOQs architecture
improves the Data Center’s performance by reducing the frames communication
latency and it is efficient with respect to the implementation cost. The current thesis
introduces a VOQs architecture for the Data Center’s ToR switches that function with
Time Division Multiple Access (TDMA). The proposed VOQs architecture contains a
bounded number of queues at each input port supporting the active destinations and
forwarding the input Ethernet frames to a shared memory buffer. An efficient mechanism
of low latency grants each queue to an active destination. The VOQs constitutes
a module of a ToR development, which is based on a commercially available Ethernet
switch and two FPGA Xilinx boards, the Virtex VC707 and the Xilinx NetFPGA. The
VOQs architecture’s implementation and validation took place on the NetFPGA board.
Moreover, the current thesis presents a management tool for the control plane’s Agent
of the Data Center. The Graphical User Interface (GUI) of the Agent’s management
tool is utilized to configure the Agent, create commands, perform step operations and
monitor the results and the status. When used as a testing and validation tool, it plays a significant role in the improvement of the Agent’s design as well as in the upgrade
of the entire Data Center’s organization and performance. Furthermore, aiming to improve
the Quality of Service (QoS) for diverse applications of the Data Center, recent
works utilize advanced Deep Learning techniques. The plethora of Machine and Deep
Learning applications involve complex processes that impose the need for hardware accelerators
to achieve real-time performance. Among these, notable are the Machine
Learning (ML) tasks using Convolutional Neural Networks (CNNs) for classification
applications.Aiming at contributing to the CNN accelerator solutions, the current thesis
focuses on the design of FPGA Accelerators for CNNs of limited feature space to improve
performance, power consumption and resource utilization, merits that ultimately
enable the use of CNNs locally at the Data Center’s ToR switches. The proposed CNN
design approach targets the designs that can utilize the logic and memory resources of
a single FPGA device and benefit numerous applications like the Edge, Mobile, Data
Center and On-board satellite (OBC) Computing. This work exploits the proposed approach
to develop an Example FPGA Accelerator for Vessel Detection, on a Xilinx
Virtex 7 XC7VX485T FPGA device. The resulting architecture achieves an operating
frequency of 270 MHz, while consuming 5 watts, it validates the approach.
Main subject category:
Science
Keywords:
FPGAs, Data Centers, Virtual Output Queues, GUI, CNN, Parallel Processing
