Unit:
Κατεύθυνση Μηχανική ΥπολογιστώνΠληροφορική
Author:
Plevris Konstantinos
Supervisors info:
Νεκτάριος Κρανίτης Αναπληρωτής Καθηγητής Τµήµα Αεροδιαστηµικής Επιστήµης και Τεχνολογίας Ε.Κ.Π.Α.
Original Title:
Architecture, Design and Implementation of a Hardware Accelerator in FPGA SoC Technology for On-Board Hyperspectral Image Data Reordering in Next Generation Earth Observation Satellites.
Translated title:
Architecture, Design and Implementation of a Hardware Accelerator in FPGA SoC Technology for On-Board Hyperspectral Image Data Reordering in Next Generation Earth Observation Satellites.
Summary:
The increasing demand for highly detailed information on human and geophysical processes on Earth has driven the development of earth observation (EO) satellite hyperspectral sensors. Hyperspectral imaging is defined as imaging narrow contiguous spectral bands over a continuous spectral range, which produces the spectra of all pixels in the scene. Hyperspectral imaging is already consolidated as a key enabling technology in remote sensing applications, used in civilian applications such as smart agriculture, geology, environmental monitoring, disaster response and recovery to name a few. However, the explosive growth of data volume of next generation high-resolution and high-speed hyperspectral remote sensing systems, compete with the limited on-board storage resources and bandwidth available for the transmission of data to ground stations, making hyperspectral image preprocessing and compression a mission critical and challenging task for on-board payload data processing. To address the above challenges components such as custom Datamovers and address generators were designed and built for reading and writing data.
This master's thesis contributes in the architecture, design and implementation of a high-performance hardware accelerator in FPGA technology, as IP core, for on-board hyperspectral image data preprocessing and especially reordering from band interleaved by pixel (BIP) order to band sequential (BSQ) order and vice-versa to be used in on-board data processing units of next generation EO satellites. The Core has been designed, implemented and validated on the Xilinx Zynq-7000 SoC ZC706 board. The goal is to achieve an acceptable throughput, considering the significant limitation in latency created by the reordering algorithm. However, the implementation presents many challenges so that the data can be reordered quickly to the opposite ordering. Furthermore, the size of a hyperspectral image can be prohibitive for local storing inside the BRAM of the FPGA, and thus the SoC's DDR memory must be used to perform the reordering. Components such as custom Datamovers and address generators for reading and writing data were designed and built to address the above challenges.
Lastly, the Zynq and MΙG (Memory interface generator) will be used for memory interfacing to buffer the intermediate data during the reordering. The interfacing for storing and retrieving the data from memory is done using the Full-AXI interface. Our design extensively uses the AXI Smartconnect for merging multiple Full-AXI interfaces as well as bridging into different interfaces for compatibility. For the BIPtoBSQ tests, by setting proper settings, we were able to achieve a cycles/sample rate of 2 for the tested cases at frequencies up to 250 and 266 MHz for the Zynq and MIG set-ups respectively. For the reverse case, smaller sized images were tested, for reasons explained below, and in some tests by setting custom settings we were able to achieve rates very close to 2. In the results section we present a variety of configurations and their impact on performance.
Main subject category:
Technology - Computer science
Keywords:
Hardware Accelerators, IP Cores, FPGA, Hyperspectral Imaging, Space Data Processing, BIP-BSQ reordering
File:
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thesis_plevris_final.pdf
3 MB
File access is restricted only to the intranet of UoA.
