System-­on-­Chip integration of a scalable hyperspectral image compression accelerator

Postgraduate Thesis uoadl:2897990 113 Read counter

Unit:
ΠΜΣ Πληροφορικής και Τηλεπικοινωνιών με ειδίκευση Τεχνολογία Συστημάτων Υπολογιστών
Πληροφορική
Deposit date:
2020-02-24
Year:
2020
Author:
Tsigkanos Antonis
Supervisors info:
Αντώνης Πασχάλης, Καθηγητής, Τμήμα Πληροφορικής και Τηλεπικοινωνιών, Εθνικό και Καποδιστριακό Πανεπιστήμιο Αθηνών
Original Title:
Ενσωμάτωση σε Σύστημα­ μιας­ Ψηφίδας ενός κλιμακώσιμου επιταχυντή συμπίεσης υπερφασματικών εικόνων
Languages:
English
Greek
Translated title:
System-­on-­Chip integration of a scalable hyperspectral image compression accelerator
Summary:
The increasing demand for highly detailed information on human and geophysical processes on Earth has driven rapid advances in Earth observation satellites equipped with hyperspectral imagers. At the same time the era of `NewSpace' has emerged in space developments, where launch costs are rapidly decreasing, and agile approaches are exploited in building small satellites using commercial-off-the-shelf parts. However, the explosive growth of data volume from high speed hyperspectral imagers compete with the limited on­board storage resources and downlink bandwidth available, making hyperspectral image compression a mission critical and challenging on-board payload data processing task. In this work we exploit the capabilities of a COTS SRAM FPGA SoC device to compress hyperspectral images at very high speed. The proposed architecture using the CCSDS 123.0-B-1 algorithm, compresses the input image cube as segments in parallel from a hyperspectral image frame­buffer in DRAM, using a software scheduler in the embedded processor to control many FPGA accelerator cores. The scheduler orchestrates DMA transactions over the on-chip bus interconnects and is designed to be integrated into a payload data processing SoC, using DRAM memory for the frame buffer in a double buffering scheme. In benchmarking on chip, the implementation reaches 447.7 Msamples/s compression throughput, with 3 cores on a Zynq-7020 device. A detailed analysis is presented on the design space exploration performed to reach high performance, in system software, RTL and SoC architecture, as well as the interplay between software and hardware.
Main subject category:
Technology - Computer science
Keywords:
Embedded Systems, Computer Hardware and Architecture, Space data systems, Data compression, Hyperspectral imaging, FPGA ac­celerator, System on Chip, SoC
Index:
Yes
Number of index pages:
5
Contains images:
Yes
Number of references:
57
Number of pages:
93

msc_thesis_antts_hyperspectral_soc.pdf
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