Unit:
Κατεύθυνση Σχεδίασης Ολοκληρωμένων ΚυκλωμάτωνΠληροφορική
Supervisors info:
Αντώνης Πασχάλης, Καθηγητής, Πληροφορικής και Τηλεπικοινωνιών, ΕΚΠΑ
Νεκτάριος Κρανίτης, Αναπληρωτής Καθηγητής, Πληροφορικής και Τηλεπικοινωνιών, ΕΚΠΑ
Original Title:
Design and Implementation in FPGA Technology of a High-Performance Block Scan and Map to Symbols Module for CCSDS-122 Image Data Compression
Translated title:
Design and Implementation in FPGA Technology of a High-Performance Block Scan and Map to Symbols Module for CCSDS-122 Image Data Compression
Summary:
Remote sensing is recognized as a cornerstone monitoring technology. The latest high ¬resolution and high-speed space-borne imagers provide an explosive growth in data volume and instrument data rates in the range of several Gbps. This competes with the limited on-board storage resources and downlink bandwidth, making image data compression a mission-critical on-board processing task.
The Consultative Committee for Space Data Systems (CCSDS) issued in 2005 a recommended standard for Image Data Compression (IDC) (CCSDS-122.0-B-1) which defines a transform-based 2D image data compression algorithm designed specifically for use on-board in a space platform or a payload. An extension of this standard, CCSDS-122.0-B-2, was issued in 2017 to define all necessary modifications to support a recommended standard for Spectral Preprocessing Transform for Multispectral and Hyperspectral Image Compression. The new issue supports images of higher dynamic range and for larger word sizes. Another recommended standard, CCSDS-122.1-B-1, was issued concurrently in 2017 to define the dedicated spectral preprocessing transforms.
In this master thesis is introduced a new high-performance architecture and implementation in FPGA technology for a key-part of the CCSDS-IDC algorithm, the submodule of the Bit Plane Encoder which implements the Block Scan and Map to Symbols process, hereafter termed BSMS, is described. The proposed architecture implementation is based on the standard’s existing parallelism, while at the same time introduces new attributes of speed, since it can process one data sample per one clock cycle and thus outperforms previous implementations that required more clock cycles.
Main subject category:
Technology - Computer science
Keywords:
Hardware Accelerator, FPGA, VHDL, Image Data Compression, CCSDS, Bit Plane Encoder
