Dissertation committee:
Αντώνης Πασχάλης, (επιβλέπων) Καθηγητής Τμήματος Πληροφορικής και Τηλεπικοινωνιών ΕΚΠΑ
Δημήτριος Γκιζόπουλος, Καθηγητής ΤμήματοςΠληροφορικής και Τηλεπικοινωνιών ΕΚΠΑ
Νεκτάριος Κρανίτης, Αναπληρωτής Καθηγητής ΤμήματοςΑεροδιαστημικής Επιστήμης και Τεχνολογίας ΕΚΠΑ
Παναγιώτης Μαθιόπουλος, Καθηγητής Τμήματος Πληροφορικής και Τηλεπικοινωνιών ΕΚΠΑ
Γεώργιος Αλεξανδρόπουλος, Επίκουρος Καθηγητής Τμήματος Πληροφορικής και Τηλεπικοινωνιών ΕΚΠΑ
Δημήτριος Σούντρης, Καθηγητής Σχολής Ηλεκτρολόγων Μηχανικών και Μηχανικών Υπολογιστών ΕΜΠ
Μιχάλης Ψαράκης, Αναπληρωτής Καθηγητής Τμήματος Πληροφορικής ΠΑΠΕΙ
Summary:
A Forward Error Correction (FEC) encoder is an integral part of an on-board processing data chain. The current Thesis deals with the problem of the design and VLSI implementation of efficient hardware encoder architectures for such systems. More specifically, two focus areas have been identified and targeted: bit-level channel coding, which is applied mostly to telemetry data transfer in near-earth and deep-space communications and packet-level erasure coding, which has emerged as a promising approach for high data rate optical space communications, or for intermittent connectivity scenarios.
Regarding the first focal point of the hereto described work, Quasi-Cyclic Low-Density Parity-Check Codes (QC-LDPC) have been adopted by the Consultative Committee for Space Data Systems (CCSDS) as recommended standard for on-board channel coding in Near-Earth and Deep-Space communications. It is shown, however, that the encoder architectures which have been so far proposed for other error-correction schemes, are either altogether inapplicable to the CCSDS QC-LDPC codes, or their direct application comes with significant performance penalties that render them inefficient for high-throughput hardware implementations. In the work presented in this thesis, a novel architecture for the multiplication of a dense QC matrix with a bit vector, which is a fundamental operation of QC-LDPC encoding, is proposed. Based on this architecture, efficient encoders for CCSDS codes are proposed, according to all the applicable LDPC encoding methods, which are analytically described and compared in terms of resource utilization efficiency for the CCSDS QC-LDPC codes. Moreover, in the special case of the specific code defined in the CCSDS standard for Near-Earth communications, specialized techniques are also introduced, which efficiently handle the challenges arising from the generator's matrix circulant size (511 bits).
The proposed architectures have been implemented in various Field Programmable Gate Array (FPGA) technologies and extensively validated and tested in the commercial counterpart of the Xilinx space-grade Kintex UltraScale XQRKU060 FPGA. The achieved performance defines the state-of-the-art in this area, being able to achieve up to more that 70 times higher encoding throughput than the corresponding implementations by NASA/JPL, on the same device and with a low resource budget. It is also the first work to introduce an extensive and realistic testing framework including modern SpaceFibre data links, in order to be as close as possible to a real mission system. Together with the detailed power measurements provided, the current work breaks untouched ground for the adoption of the CCSDS channel codes in application areas from which they had been so far considered unfavorable, due to their encoding complexity, like the upcoming high-performance Free-Space Optical space communication standards.
Protograph based QC-LDPC codes are widely considered an advantageous option for forward error correction (FEC) on magnetic recording (MR) media as well, because of their excellent performance characteristics and their inherent possibilities efficient implementation. The vast majority of related research, however, has so far been focused on the analytical optimization of code design and algorithms. Although high-speed encoding and decoding with low hardware footprint are important for MR media, hardware implementations for such encoding schemes have so far been scarce. Leveraging the architecture of LDPC encoders for space applications, efficient encoder designs for the protograph-based LDPC codes proposed for MR media are also introduced. The proposed designs are implemented in hardware as FPGA accelerators. Their efficiency is demonstrated on an FPGA development board, achieving multi-Gbps of encoding throughput, adequate for modern MR application standards. This is the first time such a study has been conducted and could prove revolutionary in the field.
Packet-level erasure coding has been considered by the CCSDS in the 131.5-O-1 experimental specification for application in high data rate near-earth and deep-space communications, since it can protect against long error bursts as they may come along with the effect of scintillation outages or transmission errors. However, implementations of packet-level encoding and decoding so far exist only in software, running on a general-purpose CPU, with limitations on the achievable performance, resource and power. In the second focus area of this work, architectures for hardware acceleration of packet-level encoding function are introduced, that allow integration on a high-speed on-board data processing chain with very low footprint and power consumption. The hardware implementations have been validated and the efficiency of the proposed architectures has been demonstrated on a Xilinx KCU105 development board, reaching an encoding throughput of over 13Gbps. Apart from offloading packet-level encoding from the on-board embedded processor, the proposed accelerators are shown to achieve a significant speedup (over 80 times), when compared with on-board software implementations of the corresponding NASA algorithms of the ION delay tolerant network (DTN) implementation, by porting on some of the most commonly used and state-of-the-art space-qualified embedded processors. This is the first documented hardware implementation of packet-level encoders and the first time that encoding throughput performance and power baselines are recorded. As with the channel codes of the first thematic area of this thesis, these findings unlock new horizons for the re-evaluation of packet-level erasure codes for use in the upcoming high-performance Free-Space Optical space communication standards.
Keywords:
Hardware Design, LDPC encoders, Hardware accelerators, Field Programmable Gate Arrays, CCSDS, Packet-Level encoders, Space Communications
