Unit:
Department of Informatics and TelecommunicationsΠληροφορική
Author:
SGOURAS KONSTANTINOS-MARIOS
Supervisors info:
Δημητρής Γκιζόπουλος, Τριτοβάθμια Βαθμίδα Εκπαίδευσης, Τμήμα Πληροφορικής και Τηλεπικοινωνιών, Εθνικό και Καποδιστριακό Πανεπιστήμιο
Original Title:
Soft Error Rate Measurements through ACE Analysis in TLB Structures of CPUs
Translated title:
Soft Error Rate Measurements through ACE Analysis in TLB Structures of CPUs
Summary:
In recent years, there has been a decrease in the minimum feature size of the transistors
in integrated circuits. As a result, the vulnerability of CPU components has increased.
An increasing rate of defects are present, causing transient faults and permanent faults.
These faults, at some point in the execution, manifest into errors that interfere with the
correctness of the execution. Thus, new ways need to be explored to (1) detect these
defects (2) correct the resulting errors or prevent the execution from being affected by
them (e.g., stopping the execution).
To this end, we studied the vulnerability of the TLB (Translation Lookaside Buffer) hierarchy in both the ARM and x86 ISA using the ACE (Architecturally Correct Execution)
methodology which applies to transient errors. We chose this component due to its criticality in the correctness of the execution (it is vital for ensuring process isolation and
security) and its frequent use, as it is responsible for caching virtual to physical translations and is accessed on every memory reference. The ACE methodology calculates the
AVF (Architectural Vulnerability Factor) of an array-based component, focusing on all of
its bits and being more pessimistic than fault injection (its alternative and standard in the
field). We conducted this study using the gem5 micro-architectural simulator. We calculated the results using benchmarks from the MiBench suite and custom stress marks.
We observed that for the x86 ISA, the average TLB hierarchy AVF from our workloads is
30.49% and the average FIT (Failures in Time) rate is 0.0226. For the ARM ISA, the average TLB hierarchy AVF from our workloads is 5.07% and the average FIT rate is 0.0414.
The differences between the two ISAs can be attributed to the L2 TLB in the case of the
ARM ISA, which drastically decreases the overall AVF but hinders the overall FIT rate due
to its size. Finally, the results reveal the pessimistic nature of the ACE methodology.
Main subject category:
Technology - Computer science
Keywords:
soft errors, vulnerability measurements, ACE, gem5, simulation, TLB
