Unit:
Department of Informatics and TelecommunicationsΠληροφορική
Author:
CHATZOPOULOS ODYSSEAS
FRAGKOULIS GEORGIOS-MARIOS
Supervisors info:
ΓΚΙΖΟΠΟΥΛΟΣ ΔΗΜΗΤΡΙΟΣ, ΚΑΘΗΓΗΤΗΣ, ΤΜΗΜΑ ΠΛΗΡΟΦΟΡΙΚΗΣ ΚΑΙ ΤΗΛΕΠΙΚΟΙΝΩΝΙΩΝ, ΕΘΝΙΚΟ ΚΑΙ ΚΑΠΟΔΙΣΤΡΙΑΚΟ ΠΑΝΕΠΙΣΤΗΜΙΟ ΑΘΗΝΩΝ
Original Title:
Evaluation of the Accuracy and the Performance of Register Transfer Level and Microarchitecture Level CPU Models
Translated title:
Evaluation of the Accuracy and the Performance of Register Transfer Level and Microarchitecture Level CPU Models
Summary:
In this work we compare RTL with microarchitecture-level simulation highlighting the performance vs accuracy trade-off between the two. In an effort to benefit from the higher speeds and flexibility of microarchitecture-level simulation while not significantly affecting simulation accuracy we strive to fine-tune the microarchitectural model to closely match the RTL one. Throughout this work we make use of the RISC-V ISA targeting a superscalar out-of-order open-source core. After going through our matching process which includes microarchitectural parameter discovery and matching followed by thorough benchmarking we achieve a 15.35% simulation error. In future work we plan to streamline the microarchitectural parameter discovery and improve simulation accuracy while also use more advanced processor and full system models.
Main subject category:
Technology - Computer science
Keywords:
computer architecture, RTL simulation, microarchitecture-level simulation, model validation, RSD, gem5
