Τίτλος:
Assessing the Effects of Low Voltage in Branch Prediction Units
Γλώσσες Τεκμηρίου:
Αγγλικά
Περίληψη:
Branch prediction units are key performance components in modern
microprocessors as they are widely used to address control hazards and
minimize misprediction stalls. The continuous urge of high performance
has led designers to integrate highly sophisticated predictors with
complex prediction algorithms and large storage requirements. As a
result, BPUs in modern microprocessors consume large amounts of power.
But when a system is under a limited power budget, critical decisions
are required in order to achieve an equilibrium point between the BPU
and the rest of the microprocessor.
In this work, we present a comprehensive analysis of the effects of low
voltage configuration Branch Prediction Units (BPU). We propose a design
with separate voltage domain for the BPU, which exploits the speculative
nature of the BPU (which is self-correcting) that allows reduction of
power without affecting functional correctness. Our study explores how
several branch predictor implementations behave when aggressively
undervolted, the performance impact of BTB as well as in which cases it
is more efficient to reduce the BP and BTB size instead of undervolting.
We also show that protection of BPU SRAM arrays has limited potential to
further increase the energy savings, showcasing a realistic protection
implementation. Our results show that BPU undervolting can result in
power savings up to 69%, while the microprocessor energy savings can be
up to 12%, before the penalty of the performance degradation overcomes
the benefits of low voltage. Neither smaller predictor sizes nor
protection mechanisms can further improve energy consumption.
Συγγραφείς:
Chatzidimitriou, Athanasios
Papadimitriou, George
Gizopoulos,
Dimitris
Ganapathy, Shrikanth
Kalamatianos, John
Εκδότης:
IEEE Comput. Soc
Τίτλος συνεδρίου:
2019 IEEE INTERNATIONAL SYMPOSIUM ON PERFORMANCE ANALYSIS OF SYSTEMS AND
SOFTWARE (ISPASS)
Λέξεις-κλειδιά:
Branch predictors; energy efficiency; gem5; microarchitectural
simulation; power; voltage scaling
DOI:
10.1109/ISPASS.2019.00020
